Interconnect delay has moved to the forefront as the limiting factor in integrated circuit performance. The recognition of interconnect delay is increasingly important as advancements in deep-submicron process geometries allow companies to build smaller, faster and less-expensive transistors. By way of example, interconnect delay may account for more than 75 percent of total path delay in a Very Large Scale Integration (VLSI) circuit. Interconnect delay is the time delay from selected input to selected output points along a given interconnect. Interconnect delay demonstrates a degree of resistance, capacitance, and to a considerably lesser degree, inductance. While the impedance might be almost negligible in a single interconnect, even an extremely small value may have a significant effect on the maximum response speed of the circuit. The delay caused by possibly millions of such interconnects in a VLSI circuit may have a profound effect on reducing the maximum operating efficiencies of the integrated circuit.